1. Field of the Invention
The present invention relates to a method of designing a standard cell type semiconductor chip and a program for use in designing a semiconductor chip. Furthermore, the present invention relates to a method of replacing a normal standard cell with a yield improvement standard cell which is prepared separately from the normal standard cell.
2. Description of the Related Art
Upon designing a standard cell type semiconductor chip, the chip yield can be improved by using a standard cell which adopts a pattern layout for improving yield (hereinafter referred to as a “yield improvement standard cell”).
A yield improvement standard cell is a standard cell whose layout is designed to reduce the number of defects as compared with a normal standard cell. For example, given that the probability of defect occurrence during a process of forming a contact hole for establishing a connection between a source or drain region of a transistor and a metal routing is p. When there are “n” contact holes in a certain standard cell, there is a possibility that “p×n” defects on average may occur in the contact holes of the standard cell. In order to reduce the average number of defects in the standard cell, the contact holes may be doubled by forming two contact holes for each contact point. In this case, the defect probability per contact point is reduced from p to the square of p. Since the order of the value of p is one several hundred millionth, the square of p can be considered to be substantially zero.
For example, when five contact holes among ten contact holes in a certain standard cell are doubled, the average number of defects in the contact holes included in the standard cell is reduced from 10 p to 5 p. The relationship between the number of defects D in a standard cell and the chip yield Y can be expressed by the following equation 1:Y=exp(−ΣD)  (1)where ΣD is the sum of the average numbers of defects in all standard cells that compose a chip (i.e., the average number of defects per chip). Thus, if the average number of defects in a chip can be reduced by reducing the number of defects in a standard cell, the chip yield is improved.
The layout of a yield improvement standard cell is created with an increased cell area such as the aforementioned doubling of contact holes. For this reason, a yield improvement standard cell is generally larger in size than a normal standard cell. Accordingly, the use of a yield improvement standard cell may increase the chip size.
Jpn. Pat. Appln. KOKAI Publication No. 11-220028 discloses that upon designing a standard cell type semiconductor chip, a replacement is performed on normal standard cells in order to improve the operating speed and to save power consumption. In this case, as basic cells all having the same function, a plurality of types of cells having different transistor channel lengths in standard cells are prepared, and a selection of which standard cell is used is made according to the purpose, whereby high-speed operation or low-power operation is made possible.